Consider two CPU scheduling algorithms for a single CPU: Round-Robin scheduling and (nonpreemptive) Shortest-Job-First scheduling. Assume that there is no time lost during context switching. Given five processes with arrival times and expected CPU time:
Process |
Arrival time |
Expected CPU time |
P1 |
0 |
14 |
P2 |
2 |
12 |
P3 |
4 |
8 |
P4 |
5 |
4 |
P5 |
17 |
7 |
a) Assuming Shortest-Job-First scheduling, draw a Gantt chart to show when each process executes on the CPU. Also compute the average waiting time.
b) Repeat for Round-Robin scheduling, assuming a time quantum of size = 6.
Consider a system with three resources (A, B, C) in quantity (9, 5, 7). The Banker's Algorithm is being used to allocate resources and it has the following current SAFE state:
Process |
Allocation |
|
Max |
|
Need |
|
Available |
|
A |
B |
C |
|
A |
B |
C |
|
A |
B |
C |
|
A |
B |
C |
P0 |
2 |
0 |
0 |
|
3 |
2 |
1 |
|
1 |
2 |
1 |
|
2 |
3 |
4 |
P1 |
0 |
1 |
0 |
|
5 |
5 |
4 |
|
5 |
4 |
4 |
P2 |
3 |
0 |
2 |
|
7 |
0 |
2 |
|
4 |
0 |
0 |
P3 |
2 |
1 |
1 |
|
2 |
2 |
1 |
|
0 |
1 |
0 |
Assume the following requests for (A, B, C) arrive in the order below.
In each case, answer YES (request granted) or NO (request denied).
Assume that the problem is CUMULATIVE.
For example, your answer for request 3 assumes that requests 1 and 2 have been processed (with results of granted or denied).
At no time during this problem are any resources actually returned by any of the processes. Show your work to support your YES/NO answers.
Request# |
Process |
Request |
Banker Response (YES/NO) |
|
|
A |
B |
C |
1 |
P1 |
2 |
3 |
4 |
YES/NO |
2 |
P0 |
1 |
2 |
1 |
YES/NO |
3 |
P3 |
1 |
1 |
1 |
YES/NO |
4 |
P3 |
0 |
1 |
0 |
YES/NO |
Design a fully simplified 3-bit mod 5 down counter with T flip-flops. The circuit decrements with each clock pulse, going through the sequence 0, 4, 3, 2, 1, 0, 4, 3, 2, 1, 0, 4, ... . Show the circuit diagram.
Design an Arithmetic Logic Unit (ALU) to perform the following operations:
S1 |
S0 |
Function |
0 |
0 |
X Plus Y |
0 |
1 |
X |
1 |
0 |
Not(Y) |
1 |
1 |
X Xor Y |
Assume that X and Y are 4-bit numbers. Draw the logic diagram of the final circuit. You should first design a 1-bit version. You may use block diagrams for full adders, half adders, multiplexers, and decoders. Use the resulting 1-bit diagram for your final result.